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61009hkim 20090409-s00002 no.a1425-1/35 semiconductor components industries, llc, 2013 july, 2013 LC75806PT overview the LC75806PT is 1/4 duty and 1/3 duty lcd display driver that can directly drive up to 304 segments and can control up to 9 general-purpos e output ports. this product al so incorporates a key scan ci rcuit that accepts input from up to 30 keys to reduce printed circuit board wiring. features ? key input function for up to 30 keys (a key scan is performed only when a key is pressed.) ? 1/4 duty 1/3 bias and 1/3 duty 1/3 bias drive schemes can be controlled from serial data. ? capable of driving up to 304 segments using 1/4 duty and up to 231 segments using 1/3 duty. ? switching between key scan output and segment output can be controlled from serial data. ? the key scan operation enabled/disabled state can be controlled from serial data. ? switching between segment output port and general-purpose output port can be controlled from serial data. ? switching between general-purpose output port, clock output port, and segment output port can be controlled from serial data. (up to 9 general-purpose output ports and up to one clock output port) ? serial data i/o supports ccb format communication with the system controller. (support 3.3v and 5v operation) ? sleep mode and all segments off functions that are controlled from serial data. ? the frame frequency of the common and segment output waveforms can be controlled from serial data. ? switching between rc oscillator operating mode and external clock operationg mode can be controlled from serial data. ? direct display of display data without the use of a decoder provides high generality. ? built-in display contrast adjustment circuit. ? provision of an on-chip voltage-detection type reset circuit prevents incorrect displays. ? res pin provided for forcibly initializing the ic internal circuits. ordering number : ena1425 cmos ic 1/4 and 1/3-duty lcd display driver with key input function http://onsemi.com ? ccb is on semiconductor? ?s original format. all addresses are managed by on semiconductor? for this format. ? ccb is a registered trademark of semiconductor components industries, llc.
LC75806PT no.a1425-2/35 specifications absolute maximum ratings at ta = 25 c, v ss = 0v parameter symbol conditions ratings unit maximum supply voltage v dd max v dd -0.3 to +7.0 v v in 1 ce, cl, di, res -0.3 to +7.0 input voltage v in 2 osc, test, v dd 1, v dd 2, ki1 to ki5 -0.3 to v dd +0.3 v v out 1 do -0.3 to +7.0 output voltage v out 2 osc, s1 to s77, com1 to com4, ks1 to ks6, p1 to p9 -0.3 to v dd +0.3 v i out 1 s1 to s77 300 a i out 2 com1 to com4 3 i out 3 ks1 to ks6 1 output current i out 4 p1 to p9 5 ma allowable power dissipation pd max ta=85 c 200 mw operating temperature topr -40 to +85 c storage temperature tstg -55 to +125 c allowable operating ranges at ta = -40 to +85 c, v ss = 0v ratings parameter symbol conditions min typ max unit supply voltage v dd v dd 4.5 6.0 v v dd 1 v dd 1 2/3v dd 0 v dd 0 input voltage *1 v dd 2 v dd 2 1/3v dd 0 v dd 0 v v ih 1 ce, cl, di, res 0.4v dd 6.0 v ih 2 ki1 to ki5 0.6v dd v dd input high level voltage v ih 3 osc: external clock operating mode 0.4v dd v dd v v il 1 ce, cl, di, res 0 0.2v dd v il 2 ki1 to ki5 0 0.2v dd input low level voltage v il 3 osc: external clock operating mode 0 0.2v dd v recommended external resistor for rc oscillation r osc osc: rc oscillation operating mode 39 k recommended external capacitor for rc oscillation c osc osc: rc oscillation operating mode 1000 pf guaranteed range of rc oscillation f osc osc: rc oscillation operating mode 19 38 76 khz external clock operating frequency f ck osc: external clock operating mode [figure4] 10 38 76 khz external clock duty cycle d ck osc: external clock operating mode [figure4] 30 50 70 % data setup time t ds cl, di [figure2], [figure3] 160 ns data hold time t dh cl, di [figure2], [figure3] 160 ns ce wait time t cp ce, cl [figure2], [figure3] 160 ns ce setup time t cs ce, cl [figure2], [figure3] 160 ns ce hold time t ch ce, cl [figure2], [figure3] 160 ns high level clock pulse width t h cl [figure2], [figure3] 160 ns low level clock pulse width t l cl [figure2], [figure3] 160 ns rise time t r ce, cl, di [figure2], [figure3] 160 ns fall time t f ce, cl, di [figure2], [figure3] 160 ns do output deley time t dc do r pu =4.7k c l =10pf *2 [figure2], [figure3] 1.5 s do rise time t dr do r pu =4.7k c l =10pf *2 [figure2], [figure3] 1.5 s note: * 1. v dd 0=0.70v dd to v dd * 2. since the do pin is an open-drain output, these times depend on the values of the pull-up resistorr pu and the load capacitance c l . stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LC75806PT no.a1425-3/35 electrical characteristics for the allowable operating ranges ratings parameter symbol pin conditions min typ max unit v h 1 ce, cl, di, res 0.03v dd hysteresis v h 2 ki1 to ki5 0.1v dd v power-down detection voltage v det 2.0 2.3 2.6 v i ih 1 ce, cl, di, res v i =6.0v 5.0 input high level current i ih 2 osc v i =v dd : external clock operating mode 5.0 a i il 1 ce, cl, di, res v i =0v -5.0 input low level current i il 2 osc v i =0v: external clock operating mode -5.0 a input floating voltage v if ki1 to ki5 0.05v dd v pull-down resistance r pd ki1 to ki5 v dd =5.0v 50 100 250 k output off leakage current i offh do v o =6.0v 6.0 a v oh 1 ks1 to ks6 i o =-500 a v dd -1.0 v dd -0.5 v dd -0.2 v oh 2 p1 to p9 i o =-1ma v dd -0.9 v oh 3 s1 to s77 i o =-20 a v dd 0-0.9 output high level voltage *1 v oh 4 com1 to com4 i o =-100 a v dd 0-0.9 v v ol 1 ks1 to ks6 i o =25 a 0.2 0.5 1.5 v ol 2 p1 to p9 i o =1ma 0.9 v ol 3 s1 to s77 i o =20 a 0.9 v ol 4 com1 to com4 i o =100 a 0.9 output low level voltage v ol 5 do i o =1ma 0.1 0.3 v v mid 1 s1 to s77 1/3 bias i o =20 a 2/3v dd 0 -0.9 2/3v dd 0 +0.9 v mid 2 s1 to s77 1/3 bias i o =20 a 1/3v dd 0 -0.9 1/3v dd 0 +0.9 v mid 3 com1 to com4 1/3 bias i o =100 a 2/3v dd 0 -0.9 2/3v dd 0 +0.9 output middle level voltage *1, *3 v mid 4 com1 to com4 1/3 bias i o =100 a 1/3v dd 0 -0.9 1/3v dd 0 +0.9 v oscillator frequency f osc osc r osc =39k , c osc =1000pf rc oscillation operating mode 30.4 38 45.6 khz i dd 1 v dd sleep mode 100 i dd 2 v dd v dd =6.0v, output open, rc oscillation operating mode, f osc =38khz 1300 2600 current drain i dd 3 v dd v dd =6.0v, output open, external clock operating mode, f ck =38khz, v ih 3=0.5v dd , v il 3=0.1v dd 1400 2800 a note: * 1. v dd 0=0.70v dd to v dd * 3. excluding the bias voltage generation divider resistor built into the v dd 0, v dd 1, v dd 2 and v ss. (see [figure 1]) [figure 1] to the common and segment drivers v dd 2 v dd 1 excluding these resistors contrast adjuster v dd v ss v dd 0
LC75806PT no.a1425-4/35 1. when cl is stopped at the low level 2. when cl is stopped at the high level 3. osc pin clock timing in external clock operating mode t dh 50% v ih 1 v ih 1 v il 1 v il 1 v ih 1 v il 1 t dr t dc t ch t cs t cp t ds t r cl t l t h t f do di d1 d0 ce [figure 2] 50% v ih 1 v il 1 t dh v ih 1 v il 1 v ih 1 v il 1 t dr t dc t ch t cs t cp t ds t f cl t h t l t r do di d1 d0 ce [figure 3] v ih 3 v il 3 osc t ckl t ckh f ck = 1 t ckh + t ckl [khz] d ck = t ckh t ckh + t ckl 100[%] 50% [figure 4]
LC75806PT no.a1425-5/35 package dimensions unit : mm (typ) 3274 pin assignment sanyo : tqfp100(14x14) 100 125 26 50 51 75 76 14.0 (1.0) (1.0) 0.1 0.125 16.0 0.2 0.5 1.2max 0.5 14.0 16.0 top view s55 s51 s52 s53 s54 s56 s57 s58 s59 s60 s61 s62 s63 s64 s65 s66 s67 s68 s69 s70 s71 s72 s73 com4/s74 com3 p5/s5 s11 p4/s4 p3/s3 p2/s2 p1/s1 com1 s76/ks2 s75/ks1 ks3 com2 LC75806PT (tqfp100) ks4 ks5 ks6 ki2 ki1 ki4 ki3 ki5 v dd s77/p9 v dd 2 v dd 1 v ss osc test res ce do cl s35 s34 s33 s32 s31 s29 s30 s27 s28 s26 di 51 75 50 76 26 100 25 1 s10 s9 p8/s8 p7/s7 p6/s6 s16 s22 s15 s14 s13 s12 s21 s20 s19 s18 s17 s25 s24 s23 s40 s39 s38 s37 s36 s45 s44 s43 s42 s41 s50 s49 s48 s47 s46
LC75806PT no.a1425-6/35 block diagram s73 com4/s74 com3 com2 com1 ce v dd di test cl do osc ki5 ki4 ki3 ki2 ki1 ks6 ks5 ks4 ks3 s76/ks2 s75/ks1 s1/p1 s2/p2 s8/p8 s9 v ss v dd 2 v dd 1 res v dd p9/s77 v dd 0 segment driver & latch general purpose port common driver contrast adjuster clock generator ccb interface control register key buffer key scan shift register vdet
LC75806PT no.a1425-7/35 pin functions symbol pin no. function active i/o handling when unused s1/p1 to s8/p8 s9 to s73 1 to 8 9 to 73 segment outputs for displaying the display data transferred by serial data input. the s1/p1 to s8/p8 pins can be used as general-purpose output ports under serial data control. - o open com1 to com3 com4/s74 77 to 75 74 common driver outputs. the frame frequency is f o [hz]. the com4/s74 pin can be used as a segment output in 1/3 duty. - o open ks1/s75 ks2/s76 ks3 to ks6 78 79 80 to 83 key scan outputs. although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced cmos transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. the ks1/s75 and ks2/s76 pins can be used as segment outputs when so specified by the control data. - o open ki1 to ki5 84 to 88 key scan inputs. these pins have built-in pull-down resistors. h i gnd p9/s77 89 general-purpose output port. this pin can be used as clock output port or segment output port under serial data control. - o open osc 95 oscillator connections. an oscillator circuit is formed by connecting an external resistor and capacitor at this pin. this pin can also be used as the external clock input pin if the external clock operating mode is selected with the control data. - i/o v dd ce 98 h i cl 99 i di 100 - i gnd do 97 serial data interface connections to the controller. note that do, being an open-drain output, requires a pull-up resistor. ce: chip enable cl: synchronization clock di: transfer data do: output data - o open res 96 reset signal input ? res=low display off - s1/p1 to s8/p8, ks1/s75, ks2/s76=low (these pins are forcibly set to the segment output port function and fixed at the low level.) - s9 to s73=low - com1 to com3=low - com4/s74=low (this pin is forcibly set to the common output function and fixed at the low level.) - p9/s77=low (this pin is forcibly set to the general-purpose output port function and fixed at the low level.) - ks3 to ks6=low - key scanning disabled - all the key data is reset to low. - osc=?z?(high impedance) - rc oscillation stopped - inhibits external clock input - display contrast adju stment circuit stopped. ? res=high display on - general-purpose output port state setting is enabled - key scanning is enabled. - rc oscillation enabled (rc oscilltator operating mode) - enables external clock input (external clock operating mode) - display contrast adjustment circuit operation is enabled. however, serial data can be transferred when the res pin is low l i v dd test 94 this pin must be connected to ground. - i - v dd 1 91 lcd drive 2/3 bias voltage (middle level) supply pin. this pin can be used to supply the 2/3 v dd 0 voltage level externally. - i open v dd 2 92 lcd drive 1/3 bias voltage (middle level) supply pin. this pin can be used to supply the 1/3 v dd 0 voltage level externally. - i open v dd 90 power supply connections. provide a voltage of between 4.5 to 6.0v. - - - v ss 93 power supply connections. connect to ground. - - -
LC75806PT no.a1425-8/35 serial data input 1. 1/4 duty (1) when cl is stopped at the low level note: b0 to b3, a0 to a3 ccb address dd direction data b1 b0 d2 d1 1 0 d74 s1 dd (3 bits) di cl ce 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 d75 0 00 ksc sc p3 p2 0 0 0 p1 k0 k1 p0 d76 d71 d72 d73 s0 pc91 pc90 oc do b1 b0 d78 d77 1 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 ct2 ct1 ct0 fc2 1 0 0 fc1 fc0 0 0 0 0 0 0 0 0 0 0 0 d152 d151 d150 d149 d148 d147 b1 b0 d229 1 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d304 d303 d302 d301 d300 d299 d230 b1 b0 d153 1 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d228 d227 d226 d225 d224 d223 d154 control data ( 17 bits ) display data (76 bits) dd (3 bits) control data ( 17 bits ) display data (76 bits) fixed data ( 17 bits ) dd (3 bits) display data (76 bits) fixed data ( 17 bits ) dd (3 bits) displa y data ( 76 bits )
LC75806PT no.a1425-9/35 (2) when cl is stopped at the high level note: b0 to b3, a0 to a3 ccb address dd direction data ? ccb addres s ?4 2h? ? d1 to d304 display data ? oc rc oscillator operating mode/external clock operationg mode switching control data ? pc90, pc91 general- purpose output port/clock output port/segment output port switching control data ? s0, s1 sleep control data ? k0, k1 key scan output/segment output switching control data ? p0 to p3 segment output port/general-purpose output port switching control data ? sc segmen t on/off control data ? ksc key scan operation enabled/disabled state setting control data ? fc0 to fc2 common and se gment output waveform frame frequency control data ? ct0 to ct2 di splay contrast setting control data 1 0 b1 b0 d2 d1 d74 s1 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 d75 0 00 ksc sc p3 p2 0 0 0 p1 k0 k1 p0 d76 d71 d72 d73 s0 pc91 pc90 oc di cl ce do ct2 ct1 ct0 fc2 1 0 0 fc1 fc0 0 0 0 0 0 0 0 0 0 0 0 d152 d151 d150 d149 d148 d147 b1 b0 d78 d77 1 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 b1 b0 b3 b2 a1 a0 a3 a2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d228 d227 d226 d225 d224 d223 1 0 0 0 0 1 0 0 d154 d153 b1 b0 1 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d304 d303 d302 d301 d300 d299 d230 d229 dd (3 bits) control data ( 17 bits ) display data (76 bits) fixed data ( 17 bits ) dd (3 bits) control data ( 17 bits ) display data (76 bits) dd (3 bits) display data (76 bits) fixed data ( 17 bits ) dd (3 bits) display data (76 bits)
LC75806PT no.a1425-10/35 2. 1/3 duty (1) when cl is stopped at the low level note: b0 to b3, a0 to a3 ccb address dd direction data b1 b0 d2 d1 1 0 d74 s1 di cl ce 0 0 0 d77 1 0 0 b3 b2 a1 a0 a3 a2 d75 0 d78 0 ksc sc p3 p2 0 0 1 p1 k0 k1 p0 d76 d71 d72 d73 s0 pc91 pc90 oc do b1 b0 d80 d79 1 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 ct2 ct1 ct0 fc2 1 0 1 fc1 fc0 0 0 0 0 0 0 0 0 0 0 0 0 d153 d152 d151 d150 d149 b1 b0 d154 1 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 d231 d230 d229 d228 d227 d226 d225 d224 d155 control data ( 18 bits ) dd (3 bits) control data ( 15 bits ) display data (78 bits) dd (3 bits) display data (75 bits) fixed data ( 15 bits ) dd (3 bits) display data (78 bits)
LC75806PT no.a1425-11/35 (2) when cl is stopped at the high level note: b0 to b3, a0 to a3 ccb address dd direction data ? ccb addres s ?4 2h? ? d1 to d231 display data ? oc rc oscillator operating mode/external clock operationg mode switching control data ? pc90, pc91 general- purpose output port/clock output port/segment output port switching control data ? s0, s1 sleep control data ? k0, k1 key scan output/segment output switching control data ? p0 to p3 segment output port/general-purpose output port switching control data ? sc segmen t on/off control data ? ksc key scan operation enabled/disabled state setting control data ? fc0 to fc2 common and se gment output waveform frame frequency control data ? ct0 to ct2 di splay contrast setting control data b1 b0 d2 d1 1 0 d74 s1 di cl ce 0 0 0 d77 1 0 0 b3 b2 a1 a0 a3 a2 d75 0 d78 0 ksc sc p3 p2 0 0 1 p1 k0 k1 p0 d76 d71 d72 d73 s0 pc91 pc90 oc do b1 b0 d80 d79 1 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 ct2 ct1 ct0 fc2 1 0 1 fc1 fc0 0 0 0 0 0 0 0 0 0 0 0 0 d153 d152 d151 d150 d149 b1 b0 1 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 d231 d230 d229 d228 d227 d226 d225 d224 d155 d154 control data ( 18 bits ) dd (3 bits) control data ( 15 bits ) display data (78 bits) dd (3 bits) displa y data ( 75 bits ) fixed data ( 15 bits ) dd (3 bits) displa y data ( 78 bits )
LC75806PT no.a1425-12/35 control data functions 1. oc ?rc oscillator operating mode/external clock operating mode switching control data this control data bit selects the osc pin function (rc oscillator operating mode or external clock operating mode) oc osc pin function 0 rc oscillator operating mode 1 external clock operating mode note: if rc oscillator operating mode is selected, connect an external resistor r osc and an external capacitor c osc to the osc pin. 2. pc90, pc91 ? general-purpose output port/clock output port/segment output port switching control data these control data bits swithes the functions of the p9/s 77 output pin between the general-purpose output port, the clock output port, and the segment output port. control data pc90 pc91 the state of p9/s77 output pin 0 0 general-purpose output port (p9) (?l? level output) 1 0 general-purpose output port (p9) (?h? level output) 0 1 clock output port (p9) (clock frequency is f osc /2 or f ck /2) 1 1 segment output port (s77) note: if the sleep mode is set, the p5/s57 output pin can not be used as the clock output port. 3. s0, s1 ? sleep control data these control data bits switch between normal mode and sleep mode, and set the states of the ks1 to ks6 key scan output during key scan standby. control data output pin states during key scan standby s0 s1 mode osc pin state (rc oscillator or acceptance of the external clock signal) segment output / common output ks1 ks2 ks3 ks4 ks5 ks6 0 0 normal operating operating h h h h h h 0 1 sleep stopped l l l l l l h 1 0 sleep stopped l l l l l h h 1 1 sleep stopped l h h h h h h note: this assumes that the ks1/s75 and ks2/s76 output pins are selected for key scan output. 4. k0, k1 ? key scan output/segment output switching control data these control data bits switch the functions of the ks1/s75 and ks2/s76 output pins between the key scan output and the segment output. control data output pin state k0 k1 ks1/s75 ks2/s56 maximum number of input keys 0 0 ks1 ks2 30 0 1 s75 ks2 25 1 x s75 s76 20 note: ksn (n=1 or 2): key scan output sn (n=75 or 76): segment output x : don't care
LC75806PT no.a1425-13/35 5. p0 to p3 ? segment output port/general-purpose output port switching control data these control data bits switch the functions of the s1/p1 to s8/p8 output pins between the segment output port and the general-purpose output port. control data output pin state p0 p1 p2 p3 s1/p1 s2/p2 s3/p3 s4/p4 s5/p5 s6/p6 s7/p7 s8/p8 0 0 0 0 s1 s2 s3 s4 s5 s6 s7 s8 0 0 0 1 p1 s2 s3 s4 s5 s6 s7 s8 0 0 1 0 p1 p2 s3 s4 s5 s6 s7 s8 0 0 1 1 p1 p2 p3 s4 s5 s6 s7 s8 0 1 0 0 p1 p2 p3 p4 s5 s6 s7 s8 0 1 0 1 p1 p2 p3 p4 p5 s6 s7 s8 0 1 1 0 p1 p2 p3 p4 p5 p6 s7 s8 0 1 1 1 p1 p2 p3 p4 p5 p6 p7 s8 1 0 0 0 p1 p2 p3 p4 p5 p6 p7 p8 note: sn (n=1 to 8): segment output port pn (n=1 to 8): general-purpose output port the table below lists the correspondence between the display da ta and the output pins when these pins are selected to be general-purpose output ports. correspondence display data output pin 1/4 duty 1/3 duty s1/p1 d1 d1 s2/p2 d5 d4 s3/p3 d9 d7 s4/p4 d13 d10 s5/p5 d17 d13 s6/p6 d21 d16 s7/p7 d25 d19 s8/p8 d29 d22 for example, if the circuit is operated in 1/4 duty and the s4/p4 output pin is selected to be a general-purpose output port, the s4/p4 output pin will output a high level when the display data d13 is 1, and will output a low level when d13 is 0. 6. sc ? segment on/off control data this control data bit controls the on/off state of the segments. sc display state 0 on 1 off however, note that when the segments ar e turned off by setting sc to 1, the segments are turned off by outputting segment off waveforms from the segment output pins. 7. ksc ? key scan operation enabled/ disabled state setting control data this control data bit enables or disables key scan operation. ksc key scan operating state 0 key scan operation enabled (a key scan operation is performed if any key on the lines corresponding to ks1 to ks6 pin which is set high is pressed.) 1 key scan operation disabled (no key scan operation is performed, even if any of the keys in the key matrix are pressed. if this state is set up, the key data is forcibly reset to 0 and the key data read request is also cleared. (do is set high.))
LC75806PT no.a1425-14/35 8. fc0 to fc2 ? common and segment output waveform frame frequency control data these control data bits set the common and segment output waveform frequency. control data fc0 fc1 fc2 frame frequency f o [hz] 1 1 0 f osc /768, f ck /768 1 1 1 f osc /576, f ck /576 0 0 0 f osc /384, f ck /384 0 0 1 f osc /288, f ck /288 0 1 0 f osc /192, f ck /192 9. ct0 to ct2 ? display contrast setting control data set the display contrast with this control data. ct0 to ct2: sets the display contrast (7 steps) ct0 ct1 ct2 lcd drive 3/3 bias voltage v dd 0 level 0 0 0 1.00v dd =v dd -(0.05v dd 0) 1 0 0 0.95v dd =v dd -(0.05v dd 1) 0 1 0 0.90v dd =v dd -(0.05v dd 2) 1 1 0 0.85v dd =v dd -(0.05v dd 3) 0 0 1 0.80v dd =v dd -(0.05v dd 4) 1 0 1 0.75v dd =v dd -(0.05v dd 5) 0 1 1 0.70v dd =v dd -(0.05v dd 6) note that although the display contrast can be adjusted by operating the built-in display contrast adjustment circuit, it can also be adjusted by modifying the supply pin v dd voltage level. display data and output pin correspondence 1. 1/4 duty output pin com1 com2 com3 com4 output pin com1 com2 com3 com4 s1/p1 d1 d2 d3 d4 s26 d101 d102 d103 d104 s2/p2 d5 d6 d7 d8 s27 d105 d106 d107 d108 s3/p3 d9 d10 d11 d12 s28 d109 d110 d111 d112 s4/p4 d13 d14 d15 d16 s29 d113 d114 d115 d116 s5/p5 d17 d18 d19 d20 s30 d117 d118 d119 d120 s6/p6 d21 d22 d23 d24 s31 d121 d122 d123 d124 s7/p7 d25 d26 d27 d28 s32 d125 d126 d127 d128 s8/p8 d29 d30 d31 d32 s33 d129 d130 d131 d132 s9 d33 d34 d35 d36 s34 d133 d134 d135 d136 s10 d37 d38 d39 d40 s35 d137 d138 d139 d140 s11 d41 d42 d43 d44 s36 d141 d142 d143 d144 s12 d45 d46 d47 d48 s37 d145 d146 d147 d148 s13 d49 d50 d51 d52 s38 d149 d150 d151 d152 s14 d53 d54 d55 d56 s39 d153 d154 d155 d156 s15 d57 d58 d59 d60 s40 d157 d158 d159 d160 s16 d61 d62 d63 d64 s41 d161 d162 d163 d164 s17 d65 d66 d67 d68 s42 d165 d166 d167 d168 s18 d69 d70 d71 d72 s43 d169 d170 d171 d172 s19 d73 d74 d75 d76 s44 d173 d174 d175 d176 s20 d77 d78 d79 d80 s45 d177 d178 d179 d180 s21 d81 d82 d83 d84 s46 d181 d182 d183 d184 s22 d85 d86 d87 d88 s47 d185 d186 d187 d188 s23 d89 d90 d91 d92 s48 d189 d190 d191 d192 s24 d93 d94 d95 d96 s49 d193 d194 d195 d196 s25 d97 d98 d99 d100 s50 d197 d198 d199 d200 note: this is for the case where the s1/p1 to s8/p8, ks1/s7 5, ks2/s76, p9/s77 output pins are selected for use as segment outputs. continued on next page.
LC75806PT no.a1425-15/35 continued from preceding page. output pin com1 com2 co m3 com4 output pin com1 com2 com3 com4 s51 d201 d202 d203 d204 s64 d253 d254 d255 d256 s52 d205 d206 d207 d208 s65 d257 d258 d259 d260 s53 d209 d210 d211 d212 s66 d261 d262 d263 d264 s54 d213 d214 d215 d216 s67 d265 d266 d267 d268 s55 d217 d218 d219 d220 s68 d269 d270 d271 d272 s56 d221 d222 d223 d224 s69 d273 d274 d275 d276 s57 d225 d226 d227 d228 s70 d277 d278 d279 d280 s58 d229 d230 d231 d232 s71 d281 d282 d283 d284 s59 d233 d234 d235 d236 s72 d285 d286 d287 d288 s60 d237 d238 d239 d240 s73 d289 d290 d291 d292 s61 d241 d242 d243 d244 ks1 /s75 d293 d294 d295 d296 s62 d245 d246 d247 d248 ks2 /s76 d297 d298 d299 d300 s63 d249 d250 d251 d252 p9/s77 d301 d302 d303 d304 note: this is for the case where the s1/p1 to s8/p8, ks1/s7 5, ks2/s76, p9/s77 output pins are selected for use as segment outputs. for example, the table below lists the segment output states for the s11 output pin. display data d41 d42 d43 d44 output pin state (s11) 0 0 0 0 the lcd segments for com1, com2, com3 and com4 are off. 0 0 0 1 the lcd segment for com4 is on. 0 0 1 0 the lcd segment for com3 is on. 0 0 1 1 the lcd segments for com3 and com4 are on. 0 1 0 0 the lcd segment for com2 is on. 0 1 0 1 the lcd segments for com2 and com4 are on. 0 1 1 0 the lcd segments for com2 and com3 are on. 0 1 1 1 the lcd segments for com2, com3 and com4 are on. 1 0 0 0 the lcd segment for com1 is on. 1 0 0 1 the lcd segments for com1 and com4 are on. 1 0 1 0 the lcd segments for com1 and com3 are on. 1 0 1 1 the lcd segments for com1, com3 and com4 are on. 1 1 0 0 the lcd segments for com1 and com2 are on. 1 1 0 1 the lcd segments for com1, com2 and com4 are on. 1 1 1 0 the lcd segments for com1, com2 and com3 are on. 1 1 1 1 the lcd segments for com1, com2, com3 and com4 are on.
LC75806PT no.a1425-16/35 2. 1/3 duty output pin com1 com2 com3 output pin com1 com2 com3 s1/p1 d1 d2 d3 s40 d118 d119 d120 s2/p2 d4 d5 d6 s41 d121 d122 d123 s3/p3 d7 d8 d9 s42 d124 d125 d126 s4/p4 d10 d11 d12 s43 d127 d128 d129 s5/p5 d13 d14 d15 s44 d130 d131 d132 s6/p6 d16 d17 d18 s45 d133 d134 d135 s7/p7 d19 d20 d21 s46 d136 d137 d138 s8/p8 d22 d23 d24 s47 d139 d140 d141 s9 d25 d26 d27 s48 d142 d143 d144 s10 d28 d29 d30 s49 d145 d146 d147 s11 d31 d32 d33 s50 d148 d149 d150 s12 d34 d35 d36 s51 d151 d152 d153 s13 d37 d38 d39 s52 d154 d155 d156 s14 d40 d41 d42 s53 d157 d158 d159 s15 d43 d44 d45 s54 d160 d161 d162 s16 d46 d47 d48 s55 d163 d164 d165 s17 d49 d50 d51 s56 d166 d167 d168 s18 d52 d53 d54 s57 d169 d170 d171 s19 d55 d56 d57 s58 d172 d173 d174 s20 d58 d59 d60 s59 d175 d176 d177 s21 d61 d62 d63 s60 d178 d179 d180 s22 d64 d65 d66 s61 d181 d182 d183 s23 d67 d68 d69 s62 d184 d185 d186 s24 d70 d71 d72 s63 d187 d188 d189 s25 d73 d74 d75 s64 d190 d191 d192 s26 d76 d77 d78 s65 d193 d194 d195 s27 d79 d80 d81 s66 d196 d197 d198 s28 d82 d83 d84 s67 d199 d200 d201 s29 d85 d86 d87 s68 d202 d203 d204 s30 d88 d89 d90 s69 d205 d206 d207 s31 d91 d92 d93 s70 d208 d209 d210 s32 d94 d95 d96 s71 d211 d212 d213 s33 d97 d98 d99 s72 d214 d215 d216 s34 d100 d101 d102 s73 d217 d218 d219 s35 d103 d104 d105 com4/s74 d220 d221 d222 s36 d106 d107 d108 ks1/s75 d223 d224 d225 s37 d109 d110 d111 ks2/s76 d226 d227 d228 s38 d112 d113 d114 p9/s77 d229 d230 d231 s39 d115 d116 d117 note: this is for the case where the s1/p1 to s8/p8, ks1/s7 5, ks2/s76, p9/s77 output pins are selected for use as segment outputs.
LC75806PT no.a1425-17/35 for example, the table below lists the segment output states for the s11 output pin. display data d31 d32 d33 output pin state (s11) 0 0 0 the lcd segments for com1, com2, and com3 are off. 0 0 1 the lcd segment for com3 is on. 0 1 0 the lcd segment for com2 is on. 0 1 1 the lcd segments for com2 and com3 are on. 1 0 0 the lcd segment for com1 is on. 1 0 1 the lcd segments for com1 and com3 are on. 1 1 0 the lcd segments for com1 and com2 are on. 1 1 1 the lcd segments for com1, com2 and com3 are on. serial data output 1. when cl is stopped at the low level 2. when cl is stopped at the high level ? ccb address ?4 3h? ? kd1 to kd30 key data ? sa sleep acknowledge data note: if a key data read operation is executed when do is hi gh (do does not generate a key data read request output), the read key data (kd1 to kd30) and sleep acknowledge data (sa) will be invalid. ce a3 a2 a1 a0 b3 b2 b1 b0 kd2 kd1 x sa kd30 kd29 kd28 kd27 0 1 do di cl output data note: b0 to b3, a0 to a3 ? ccb address x: don?t care 1 0 0 0 0 1 ce a3 a2 a1 a0 b3 b2 b1 b0 kd2 kd1 xx kd30 kd29 kd28 0 1 do di cl output data note: b0 to b3, a0 to a3 ? ccb address x: do n?t ca r e 1 0 0 0 0 1 kd3 sa
LC75806PT no.a1425-18/35 output data 1. kd1 to kd30 ? key data when a key matrix of up to 30 keys is formed from the ks1 to ks6 output pins and ki1 to ki5 input pins and one of those keys is pressed, the key output data corresponding to that key will be set to 1. the table shows the relationship between those pins and the key data bits. ki1 ki2 ki3 ki4 ki5 ks1/s75 kd1 kd2 kd3 kd4 kd5 ks2/s76 kd6 kd7 kd8 kd9 kd10 ks3 kd11 kd12 kd13 kd14 kd15 ks4 kd16 kd17 kd18 kd19 kd20 ks5 kd21 kd22 kd23 kd24 kd25 ks6 kd26 kd27 kd28 kd29 kd30 when the ks1/s75 and ks2/s76 output pins are selected to be segment outputs by control data bits k0 and k1 and a key matrix of up to 20 keys is formed using the ks3 to ks6 output pins and the ki1 to ki5 input pins, the kd1 to kd10 key data bits will be set to 0. 2. sa ? sleep acknowledge data this output data bit is set to the state when the key was presse d. also, while do will be low in this case, if serial data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. sa will be 1 in sleep mode and 0 in normal mode. sleep mode functions sleep mode is set up by setting s0 or s1 in the control data to 1. when sleep mode is set up, both the segment and common outputs will go to the low level. in rc oscillator operating mode (oc=0), the os cillator on the osc pin will stop (although it will operate during key scan operations), and in exeternal clock operat ing mode (oc=1), acceptance of the external clock signal on the osc pin will stop (although the clock signal will be accepted during key scan operations). thus this mode reduces power consumption. howeve r, the s1/p1 to s8/p8, p9/s77 output pins can be used as general-purpose output ports under control of the p0 to p3, pc90 and pc91 bits in the control data even in sleep mode (the p9/s77 output pin can not be used as clock output port). sleep mode is cancelled by setting both s0 and s1 in control data to 0. key scan operation functions 1. key scan timing the key scan period is 288t[s]. to reliably determine the on/off state of the keys, the LC75806PT scans the keys twice and determines that a key has been pressed when the key data agrees. it outputs a key data read request (a low level on do) 615t[s] after starting a key scan. if the key data does not agree and a key was pressed at that point, it scans the keys again. thus the LC75806PT cannot detect a key press shorter than 615t[s]. note: * 4. these are set to the high or low level by the s0 and s1 bits in the control data. key scan output signals are not output from pins that are set to the low level. key on 576t[s] *4 *4 *4 *4 *4 *4 *4 *4 *4 1 1 2 2 3 3 4 4 5 5 6 6 ks4 ks5 ks6 ks3 ks2 *4 ks1 t= = 1 f osc 1 f ck
LC75806PT no.a1425-19/35 2. normal mode, when key scan operations are enabled (1) the ks1 to ks6 pins are set high. (see the description of the control data.) (2) when a key is pressed, a key scan is started and th e keys are scanned until all keys are released. multiple key presses are recognized by determining whether multiple key data bits are set. (3) if a key is pressed for longer than 615t[s] (where t=1/f osc or t=1/f ck ), the LC75806PT outputs a key data read request (a low level on do) to the controller. the cont roller acknowledges this request and reads the key data. however, if ce is high during a serial data transfer, do will be set high. (4) after the controller reads the key data, the key data re ad request is cleared (do is set high) and the LC75806PT performs another key scan. also note that do, being an open-drain output, requires a pull-up resistor (between 1 and 10k ). 3. sleep mode, when key s can operations are enabled (1) the ks1 to ks6 pins are set to high or low level by the s0 and s1 bits in the control data. (see the description of the control data.) (2) if a key on one of the lines corresponding to a ks1 to ks6 pin which is set high is pressed, the oscillator on the osc pins starts in rc oscillator operating mode (the ic star ts accepting the external clock signal in external clock operating mode) and a key scan is performed. keys are scanned until all keys are released. multiple key presses are recognized by determin ing whether multiple key data bits are set. (3) if a key is pressed for longer than 615t[s] (where t=1/f osc or t=1/f ck ), the LC75806PT outputs a key data read request (a low level on do) to the controller. the cont roller acknowledges this request and reads the key data. however, if ce is high during a serial data transfer, do will be set high. (4) after the controller reads the key data, the key data read request is cleared (do is set high) and the LC75806PT performs another key scan. however, this does not clear sleep mode. also note that do, being an open- drain output, requires a pull-up resistor (between 1 and 10k ? ). (5) sleep mode key scan example example: s0=0, s1=1 (sleep with only ks6 high) note: * 5. these diodes are required to reliably recognize multiple key presses on the ks6 line when sleep mode state with only ks6 high, as in the above example. that is, these diodes prevent incorrect operations due to sneak currents in the ks6 key scan output signal when keys on the ks1 to ks5 lines are pressed at the same time. serial data transfer key data read request key data read do di key address(43h) ce key scan key input 2 key input 1 615t[s] 615t[s] (ksc=0) 615t[s] serial data transfer (ksc=0) serial data transfer (ksc=0) key address key address key data read request key data read key data read key data read request ki1 ki2 ki3 ki4 ki5 *5 ?l? ks3 ?h? ks6 ?l? ks2 when any one of these keys is pressed, the oscillator on the osc pins starts in rc oscillator operating mode (the ic starts accepting the external clock signal in external clock operating mode) and a key scan operation is performed . ?l? ks1 ?l? ks4 ?l? ks5 t= = 1 f osc 1 f ck
LC75806PT no.a1425-20/35 4. normal/sleep mode, when key scan operations are disabled (1) the ks1 to ks6 pins are set to high or low level by the s0 and s1 bits in the control data. (2) no key scan operation is performed, whichever key is pressed. (3) if the key scan disabled state (ksc=1 in the control data) is set during a key scan, the key scan is stopped. (4) if the key scan disabled state (ksc=1 in the control data) is set when a key data read request (a low level on do) is output to the controller, all the key data is set to 0 and the key data read request is cleared (do is set high). note that do, being an open-drain output, requires a pull-up resister (between 1 to 10k ). (5) the key scan disabled state is cleared by setting ksc in the control data to 0. multiple key presses although the LC75806PT is capable of key scanning without inserting diodes for dual key presses, triple key presses on the ki1 to ki5 input pin lines, or multiple key presses on the ks1 to ks6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recogni zed as having been pressed. therefore, a diode must be inserted in series with each key. appli cations that do not recognize multiple ke y presses of three or more keys should check the key data for three or more 1 bits and ignore such data. do di ce key scan key input (ks6 line) 615t[s] 615t[s] (ksc=0) (ksc=0) (ksc=0) key data read request key data read serial data transfer serial data transfer key address key data read key data read request serial data transfer key address(43h) do di ce key scan key input 2 615t[s] 615t[s] (ksc=0) (ksc=0) (ksc=1) key input 1 (ksc=0) (ksc=1) key data read request key data read key address(43h) serial data transfer serial data transfer serial data transfer serial data transfer serial data transfer key data read request t= = 1 f osc 1 f ck t= = 1 f osc 1 f ck
LC75806PT no.a1425-21/35 1/4 duty, 1/3 bias drive technique control data fc0 fc1 fc2 common and segment output waveform frame frequency f o [hz] 1 1 0 f osc /768, f ck /768 1 1 1 f osc /576, f ck /576 0 0 0 f osc /384, f ck /384 0 0 1 f osc /288, f ck /288 0 1 0 f osc /192, f ck /192 com3 com2 com1 com4 lcd driver output when all lcd segments corresponding to com1, com2, com3, and com4 are on. lcd driver output when lcd segments corresponding to com2 and com4 are on. lcd driver output when only lcd segments corresponding to com4 are on. lcd driver output when lcd segments corresponding to com1, com2, and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when only lcd segments corresponding to com1 are on. lcd driver output when all lcd segments corresponding to com1, com2, com3, and com4 are turned off. v dd 1 v dd 2 f o [hz] v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v
LC75806PT no.a1425-22/35 1/3 duty, 1/3 bias drive technique control data fc0 fc1 fc2 common and segment output waveform frame frequency f o [hz] 1 1 0 f osc /768, f ck /768 1 1 1 f osc /576, f ck /576 0 0 0 f osc /384, f ck /384 0 0 1 f osc /288, f ck /288 0 1 0 f osc /192, f ck /192 com3 com2 com1 lcd driver output when all lcd segments corresponding to com1, com2, and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when only lcd segments corresponding to com1 are on. lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. lcd driver output when all lcd segments corresponding to com1, com2, and com3 are turned off. v dd 1 v dd 2 f o [hz] v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v
LC75806PT no.a1425-23/35 clock signal output waveform control data pc90 pc91 the state of p9/s77 output pin 0 1 clock output port (p9) (clock frequency is f osc /2 or f ck /2) voltage detection type reset circuit (v det ) this circuit generates an output signal and resets the system when power is first applied and when the voltage drops, i.e., when the power supply voltage is less than or equal to the power down detection voltage v det , which is 2.3v, typical. to assure that this function operates reliably, a capacitor mu st be added to the power supply line so that the power supply voltage v dd rise time when the power is first a pplied and the power supply voltage v dd fall time when the voltage drops are both at least 1ms. (see figure 5 and figure 6.) system reset the LC75806PT supports the reset methods described below. when a system reset is applied, display is turned off, key scanning is stopped, all the key data is reset to low, and th e general-purpose output ports are fixed at the low level (the s1/p1 to s8/p8 pins are forcibly set to the segment output port function and fixed at the low level. the p9/s77 pin is forcibly set to the general-purpose output port function and fixe d at the low level). when the reset is cleared, display is turned on, key scanning is enabled and the general-purpose output ports state setting is enabled. 1. reset methods (1) reset method by the voltage detection type reset circuit (v det ) if at least 1ms is assured as the supply voltage v dd rise time when power is applied, a system reset will be applied by the v det output signal when the supply voltage is brought up. if at least 1 ms is assured as the supply voltage v dd fall time when power drops, a system reset will be applied in the same manner by the v det output signal when the supply voltage is lowered. note that the reset is cl eared at the point when all th e serial data (1/4 duty: the display data d1 to d304 and the control data, 1/3 duty: the display data d1 to d231 and the control data) has been transferred, i.e., on the fall of the ce signal on the transfer of th e last direction data, after all the direction data has been transferred. (see figure 5 and figure 6.) ? 1/4 duty p9 tc tc/2 1 fc tc= display and control data transfer d1 to d76 internal data oc, pc90, pc91, s0, s1, k0, k1, p0 to p3, sc, ksc internal data d77 to d152, fc0 to fc2, ct0 to ct2 internal data (d153 to d228) v dd ce system reset period undefined defined [figure 5] note: t1 1 [ms](power supply voltage v dd rise time) t2 1 [ms](power supply voltage v dd fall time) v il 1 internal data (d229 to d304) t2 t1 v det v det undefined undefined undefined defined defined defined undefined undefined undefined undefined
LC75806PT no.a1425-24/35 ? 1/3 duty (2) reset method by the res pin when power is applied, a system reset is applied by setting the res pin low level. the reset is cleared by setting the res pin high level after all the serial data (1/4 duty: the display data d1 to d304 and the control data, 1/3 duty: the display data d1 to d231 and the control data) has been transferred. in the allowable operating range (v dd =4.5 to 6.0v), a reset is applied by setting the res pin low level. and the reset is cleared by setting the res pin high level. 2. internal block states during the reset period ? clock generator a reset is applied and either the osc pin oscillator is stopped or external clock reception is stopped ? common driver, segment driver & latch a reset is applied and the display is turned off. however, di splay data can be input to the latch circuit in this state. ? contrast adjuster a reset is applied and the display contrast adjustment circuit operation is disabled. ? key scan a reset is applied, the circuit is set to the initial state, and at the same time the ke y scan operation is disabled. ? key buffer a reset is applied and all the key data is set to low. ? general purpose port a reset is applied, the circuit is set to the initial state. ? ccb interface, shift register, control register since serial data transfer is possi ble, these circuits are not reset. [figure 6] display and control data transfer d1 to d78 internal data oc, pc90, pc91, s0, s1, k0, k1, p0 to p3, sc, ksc internal data (d154 to d231) v dd ce system reset period undefined defined v il 1 t2 t1 v det v det note: t1 1 [ms](power supply voltage v dd rise time) t2 1 [ms](power supply voltage v dd fall time) undefined undefined undefined undefined undefined defined defined internal data d79 to d153, fc0 to fc2, ct0 to ct2
LC75806PT no.a1425-25/35 blocks that are reset s73 com4/s74 com3 com2 com1 ce v dd di test cl do osc ki5 ki4 ki3 ki2 ki1 ks6 ks5 ks4 ks3 s76/ks2 s75/ks1 s1/p1 s2/p2 s8/p8 s9 v ss v dd 2 v dd 1 res v dd p9/s77 v dd 0 segment driver & latch general purpose port common driver contrast adjuster clock generator ccb interface control register key buffer key scan shift register vdet
LC75806PT no.a1425-26/35 3. pin states during the reset period pin state during reset s1/p1 to s8/p8 l *6 s9 to s73 l com1 to com3 l com4/s74 l *7 ks1/s75, ks2/s76 l *6 ks3 to ks6 l *8 p9/s77 l *9 osc z *10 do h *11 note: * 6. these output pins are forcibly set to the segment output function and held low. * 7. this output pin is forcibly set to the common output function and held low. * 8. these output pins are forcibly held fixed at the low level. * 9. this output pin is forcibly set to the general-purpose output port function and held low. * 10. this i/o pin is forcibly set to the high-impedance state. * 11.since this output pin is an open-drain output, a pull-up resistor of between 1 and 10k is required. this pin remains high during the reset period even if a key data read operation is performed. notes on the osc pin peripheral circuit 1. rc oscillator operationg mode (control data bit oc=0) when rc oscillator operationg mode is selected, an external resistor r osc and an external capacitor c osc must be connected between the osc pin and gnd. 2. external clock operating mode (control data bit oc=1 ) when selecting the external clock operating mode, connect a current protection resistor rg (4.7 to 47k ) between the osc pin and the external clock output pin (external oscillator). determine the value of the resistance according to the maximum allowable current value of the external clock output pin. also make sure that the waveform of the external clock is not excessively distorted. osc external clock output pin rg external oscillator note: allowable current value at external clock output pin > v dd rg osc c osc r osc
LC75806PT no.a1425-27/35 sample application circuit 1 1/4 duty, 1/3 bias note: * 12. add a capacitor to the power supply line so that the power supply voltage v dd rise time when power is applied and the power supply voltage v dd fall time when power drops ar e both at least 1ms, as the LC75806PT is reset by the v det . * 13. if the res pin is not used for system reset, it must be connected to the power supply v dd . * 14. when rc oscillator operating mode is used, the external resistor r osc and the external capacitor c osc must be connected between the osc pin and gnd, and wh en external clock operatin g mode is selected the current protection resistor rg (4.7 to 47k ) must be connected between the osc pin and the external clock output pin (external oscillator). (see the section on the osc pin peripheral circuit.) * 15. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1 to 10k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. * 16. the pins to be connected to the controller (ce, cl, di, do, res ) can handle 3.3v or 5v. c 0.047
LC75806PT no.a1425-28/35 sample application circuit 2 1/3 duty, 1/3 bias note: * 12. add a capacitor to the power supply line so that the power supply voltage v dd rise time when power is applied and the power supply voltage v dd fall time when power drops ar e both at least 1ms, as the LC75806PT is reset by the v det . * 13. if the res pin is not used for system reset, it must be connected to the power supply v dd . * 14. when rc oscillator operating mode is used, the external resistor r osc and the external capacitor c osc must be connected between the osc pin and gnd, and wh en external clock operatin g mode is selected the current protection resistor rg (4.7 to 47k ) must be connected between the osc pin and the external clock output pin (external oscillator). (see the section on the osc pin peripheral circuit.) * 15. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1 to 10k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. * 16. the pins to be connected to the controller (ce, cl, di, do, res ) can handle 3.3v or 5v. notes on transferring display data from the controller when using the LC75806PT in 1/4 duty, applications transfer the display data (d1 to d304) in four operations, and in 1/3 duty, they transfer the display data (d1 to d231) in three operations. in either case, app lications should transfer all of the display data within 30ms to maintain the quality of displayed image. c 0.047
LC75806PT no.a1425-29/35 notes on the controller key data read techniques 1. timer based key data acquisition (1) flowchart (2) timing chart t3 key scan execution time when the key data agreed for two key scans. (615t[s]) t4 key scan execution time when the key data did no t agree for two key scans and the key scan was executed again. (1230t[s]) t5 key address (43h) transfer time t6 key data read time (3) explanation in this technique, the controller uses a timer to determ ine key on/off states and read the key data. the controller must check the do state when ce is low every t7 period without fail. if do is low, the controller recognizes that a key has been pressed and executes the key data read operation. the period t7 in this technique must satisfy the following condition. t7>t4+t5+t6 if a key data read operation is executed when do is high (do does not generate a key data read request output), the read key data (kd1 to kd30) and sleep acknowledge data (sa) will be invalid. key data read processing yes no do=?l? ce=?l? controller determination (key on) key data read request key data read do di ce key on key on key address key scan key input t4 t7 t7 t7 t7 t3 t6 t6 t5 t5 t3 t5 t6 t3 controller determination (key on) controller determination (key off) controller determination (key on) controller determination (key off) t= = 1 f osc 1 f ck
LC75806PT no.a1425-30/35 2. interrupt based key data acquistion (1) flowchart (2) timing chart t3 key scan execution time when the key data agreed for two key scans. (615t[s]) t4 key scan execution time when the key data did no t agree for two key scans and the key scan was executed again. (1230t[s]) t5 key address (43h) transfer time t6 key data read time (3) explanation in this technique, the controller uses interrupts to determine key on/off states and read the key data. the controller must check the do state wh en ce is low. if do is low, the c ontroller recognizes that a key has been pressed and executes the key data read operation. after that the next key on/off determination is performed after the time t8 has elapsed by checking the do state when ce is low and reading the key data. the period t8 in this technique must satisfy the following condition. t8>t4 if a key data read operation is executed when do is high (do does not generate a key data read request output), the read key data (kd1 to kd30) and sleep acknowledge data (sa) will be invalid. controller determination (key on) key data read request key data read do di ce key on key on key address key scan key input t8 t8 t8 t8 t3 t4 t6 t6 t5 t5 t3 t5 t6 t3 t5 t6 controller determination (key off) controller determination (key on) controller determination (key on) controller determination (key on) controller determination (key off) key data read processing yes yes no do=?l? ce=?l? wait for at least t8 key off no ce=?l? do=?h? t= = 1 f osc 1 f ck
LC75806PT no.a1425-31/35 about data communication me thod with the controller 1. about data communication method of 4 line type ccb format the 4 line type ccb format is the data communication method of before. the LC75806PT must connect to the controller as followings. 2. about data communication method of 3 line type ccb format the 3 line type ccb format is the data communication method that made a common use of the data input di in the data output do. the LC75806PT must connect to the controller as followings. in this case, applications must transfer the data comm unication start command before the serial data input (ccb address ?42h?, display data and control da ta transfer) or serial data output ( ccb address ?43h? transfer, key data read) to avoid the collision of the data input signal di and the data output signal do. then applications must transfer the data communication stop command when the controller wants to detect the key data read request signal (a low level on do) during a movement stop of the serial data input and the serial data output. < 1 > data communication start command (1) when cl is stopped at the low level (2) when cl is stopped at the high level < 2 > data communication stop command (1) when cl is stopped at the low level (2) when cl is stopped at the high level note: *17. connect the pull-up resistor rup. select a resistance (between 1 to 10k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *18. the (int) pin is an input port for the key data read request signal (a low level on do) detection. do di cl ce di do cl ce rup LC75806PT controller (int) *18 *17 do di cl ce dio cl ce rup LC75806PT controller note: *17. connect the pull-up resistor rup. select a resistance (between 1 to 10k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *18. the (int) pin is an input port for the key data read request signal (a low level on do) detection. (int) *17 *18 0 0 0 0 1 ccb address ?00h? di/do cl ce 0 0 0 0 0 0 1 1 1 1 0 command data 0 0 0 01 di / do cl ce 0 0 00 0 011 1 1 0 ccb address ?00h? command data 1 1 0 0 1 di/do cl ce 0 0 0 0 0 0 1 1 0 0 0 ccb address ?00h? command data 1 1 0 01 di / do cl ce 0 0 00 0 011 0 0 0 ccb address ?00h? command data
LC75806PT no.a1425-32/35 data communication flowchart of 4 li ne type or 3 line type ccb format 1. flowchart of the initial setting when power is turned on. 2. flowchart of the serial data input 3. flowchart of the serial data output data communication start command transfer serial data output (key data and sleep acknowledge data read) the controller acknowledges the key data read request (when the ce is low, the do is low) yes no note: *20. in the case of the 4 line type ccb format, the transfer of data communication start command is unnecessary, and, in the case of the 3 line type ccb format, the transfer is necessary. *21. because the serial data output has the role of the data communication stop command, it is not necessary to transfer the data communication stop command some other time. *20 *21 data communication start command transfer yes serial data input (display and control data transfer) data communication stop command transfe r the controller wants to detect the key data read request signal ( a low level on do ) . no *19 *19 note: *19. in the case of the 4 line type ccb format, the transfers of data communication start command and data communication stop command are unnecessary, and, in the case of the 3 line type ccb format, these transfers are necessary. power on (applications must observe that the power supply v dd rise time is at least 1ms.) serial data input (display and control data transfer) power supply stability (applications must wait till the level of the power supply is stable) system reset clear (display on, key scanning is enabled, general-purpose output port state setting are enabled) note: the flowchart of initial setting when power is turned on is same regardless of the 4 line type or 3 line type ccb format. take explanation about "system reset" into account.
LC75806PT no.a1425-33/35 timing chart of 4 line type and 3 line type ccb format 1. timing chart of 4 line type ccb format < example 1 > < example 2 > < example 3 > note: * 22. when the key data agrees for two key scans, the key scan execution time is 615t[s]. and, when the key data does not agree for two key scans and the key scan is executed again, the key scan exec ution time is 1230t[s]. di ce key on key off key scan key input serial data input (display and control data transfer) serial data output (key data read) key data read request key data read request key scan execution *22 do ccb address (42h) ccb address (42h) ccb address (42h) ccb address (43h) key scan execution *22 di ce key on key scan key input serial data input (display and control data tranfer) serial data output (key data read) key data read request key data read request key on key off key off do serial data output (key data read) key scan execution *22 key scan execution *22 ccb address (43h) ccb address (43h) di ce key on key scan key input serial data input (display and control data transfer) serial data output (key data read) key data read request key data read request key off serial data output (key data read) key off do key scan execution *22 key scan execution *22 ccb address (42h) ccb address (42h) ccb address (42h) ccb address (43h) ccb address (43h) ccb address (42h) ccb address (42h) ccb address (42h) ccb address (42h) ccb address (42h) ccb address (42h) t= = 1 f osc 1 f ck
LC75806PT no.a1425-34/35 2. timing chart of 3 line type ccb format < example 1 > < example 2 > < example 3 > note: * 22. when the key data agrees for two key scans, the key scan execution time is 615t[s]. and, when the key data does not agree for two key scans and the key scan is executed again, the key scan exec ution time is 1230t[s]. di/do ce key on key off key scan key input data communication start command serial data input (display and control data transfer) data communication stop command data communication start command serial data output (key data read) key data read request key data read request ccb address (42h) key scan execution *22 key scan execution *22 ccb address (42h) ccb address (42h) ccb address (43h) di/do ce key on key scan key input data communication start command serial data input (display and control data transfer) data communication stop command data communication start command serial data output (key data read) key data read request key data read request key on key off key off data communication start command serial data output (key data read) key scan execution *22 key scan execution *22 ccb address (42h) ccb address (42h) ccb address (42h) ccb address (43h) ccb address (43h) di/do ce key on key scan key input data communication start command serial data input (display and control data transfer) serial data output (key data read) key data read request key data read request key off serial data output (key data read) key off key scan execution *22 key scan execution *22 ccb address (42h) ccb address (42h) ccb address (43h) ccb address (43h) ccb address (42h) data communication start command ccb address (42h) ccb address (42h) ccb address (42h) t= = 1 f osc 1 f ck
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